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Nishikawa, Hiroaki. Pipeline stage-level simulation method for self-timed data-driven processor on FPGA. (). King Mongkut's University of Technology North Bangkok. Central Library. : , 2020.
Pipeline stage-level simulation method for self-timed data-driven processor on FPGA
Name: Yoshikawa, Senri
Organization :
University of Tsukuba. School of Informatics
Email :
yoshikawa@coins.tsukuba.ac.jp
Name: Sannomiya, Shuji
Organization :
University of Tsukuba. Faculty of Engineering, Information and Systems
Email :
san@cs.tsukuba.ac.jp
Name: Iwata, Makoto
Organization :
Kochi University of Technology. School of Information
Email :
iwata.makoto@kochi-tech.ac.jp
Name: Nishikawa, Hiroaki
Organization :
University of Tsukuba. Headquarters for International Industry-University Collaboration
Email :
nisikawa@cs.tsukuba.ac.jp
keyword:
Data-driven architecture
LCSH:
Asynchronous circuits
Abstract:
This paper describes an FPGA circuit simulation
method for self-timed data-driven processor with ultra-low-power
real-time multiprocessing capability preferable to IoT systems. To
avoid the do-overs of circuit design, the processors performance
should be verified, in early design phase, against a given target.
Although this processor is realized by an asynchronous circuit,
most FPGA devices are oriented to clock-synchronized circuits
and their CAD tools have no support for such high level
verification. Conventionally, a gate-level simulation with actual
circuit delay information is used as a substitute; however, it lacks
flexibility and is becoming unavailable. Already, asynchronous
circuit design methods for FPGA have been proposed, but they
are primarily focused on circuit implementation and optimization.
In this paper, we propose a high level simulation method to
provide RTL simulation with stage-by-stage data transfer timing,
and we show the proposed simulation can achieve the early design
phase verification with a sufficient accuracy.
King Mongkut's University of Technology North Bangkok. Central Library
Address:
BANGKOK
Email:
library@kmutnb.ac.th
Created:
2020
Modified:
2026-01-15
Issued:
2026-01-15
บทความ/Article
application/pdf
BibliograpyCitation :
In Electrical Engineering Academic Association (Thailand). 2020 8th International Electrical Engineering Congress (iEECON 2020) (pp.199-203). Red Hook, NY : Institute of Electrical and Electronics Engineers
eng
©copyrights King Mongkut's University of Technology North Bangkok
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0.039413 วินาที
Yoshikawa, Senri
| Title | Contributor | Type |
|---|---|---|
| Pipeline stage-level simulation method for self-timed data-driven processor on FPGA
มหาวิทยาลัยเทคโนโลยีพระจอมเกล้าพระนครเหนือ Yoshikawa, Senri;Sannomiya, Shuji;Iwata, Makoto;Nishikawa, Hiroaki | บทความ/Article |
Sannomiya, Shuji
| Title | Contributor | Type |
|---|---|---|
| Pipeline stage-level simulation method for self-timed data-driven processor on FPGA
มหาวิทยาลัยเทคโนโลยีพระจอมเกล้าพระนครเหนือ Yoshikawa, Senri;Sannomiya, Shuji;Iwata, Makoto;Nishikawa, Hiroaki | บทความ/Article |
Iwata, Makoto
| Title | Contributor | Type |
|---|---|---|
| Pipeline stage-level simulation method for self-timed data-driven processor on FPGA
มหาวิทยาลัยเทคโนโลยีพระจอมเกล้าพระนครเหนือ Yoshikawa, Senri;Sannomiya, Shuji;Iwata, Makoto;Nishikawa, Hiroaki | บทความ/Article |
Nishikawa, Hiroaki
| Title | Contributor | Type |
|---|---|---|
| Pipeline stage-level simulation method for self-timed data-driven processor on FPGA
มหาวิทยาลัยเทคโนโลยีพระจอมเกล้าพระนครเหนือ Yoshikawa, Senri;Sannomiya, Shuji;Iwata, Makoto;Nishikawa, Hiroaki | บทความ/Article |