BIST design and implementation for a fixed-point arithmetic MAC unit within a systolic array

Name: Grout, Ian

Organization : University of Limerick. Department of Electronic and Computer Engineering

Email : Ian.Grout@ul.ie

keyword: MAC

ThaSH: Machine learning

; FPGA

ThaSH: Systolic array circuits

ThaSH: Electronic data processing

Abstract: In embedded systems involving hardware accelerators to support embedded machine learning (ML) applications, both sequential and parallel operations are used to ensure the system can perform its required operations in the required time. For ML applications involving trained ML model inference, parallel (concurrent) hardware structures can be utilized to perform parallel multiplications usually involving matrix multiplication operations in hardware rather than software. In this paper, fault simulation, embedded instrument test access and built-in self-test (BIST) are considered in relation to the multiply-accumulate (MAC) unit that would be found within a systolic array. A fault simulation was performed on the pre-synthesis MAC unit Verilog HDL design module and used to develop a BIST unit accessible via an IEEE Std 1687 network. The design was prototyped using a Xilinx Artix-7 field programmable gate array (FPGA).

King Mongkut's University of Technology North Bangkok. Central Library

Address: BANGKOK

Email: library@kmutnb.ac.th

Created: 2023

Modified: 2024-12-03

Issued: 2024-12-03

บทความ/Article

application/pdf

BibliograpyCitation : In Electrical Engineering Academic Association (Thailand), Mahasarakham University. Faculty of Engineering and ASEFA. The 2023 International Electrical Engineering Congress (iEECON 2023) (pp.113-116). Mahasarakham : Mahasarakham University

eng

©copyrights King Mongkut's University of Technology North Bangkok

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