Abstract:
This research aimed to develop and validate the efficiency of instruction media
and activity integrated with SEDEA learning model on the topic of Electrical circuit
analysis. Research methodology step were; the development of integration learning
activity with SEDEA learning model, the development of computer program simulation,
the construct achievement test, experiment, collect and analyse data. Samples were 12
students of the Rajamangala University of Technology Srivijaya, Rattaphum Collage,
who registered in Fundamental of Electrical Engineering course in the second semester
of 2010.
The research results were as follows. The instruction media and activity integrated
with SEDEA learning model on electrical circuit analysis had efficiency at 81.53/80.14
which was higher than criterion 80/80. The mean of student satisfaction on the constructed
instruction was high level.